System-on-Chip (SoC) designs often include several application specific peripherals integrated with a direct memory access (DMA) unit. The DMA unit allows these peripherals to transfer data without a high degree of intervention by the central processing unit (CPU). Peripherals initiate read/write transfers as required. A bus bridge arbitrates and grants control of the bus to one peripheral. Since the effective utilization of DMA bandwidth determines the overall system performance, it is very important that the peripherals never throttle throughput by halting transfers through deactivation of the ready/acknowledge signal after getting control of the bus.